Xilinx Design Summary

AVP Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	504	26,624	1%
Number of 4 input LUTs	1,036	26,624	3%
Logic Distribution
Number of occupied Slices	697	13,312	5%
Number of Slices containing only related logic	697	697	100%
Number of Slices containing unrelated logic	0	697	0%
Total Number of 4 input LUTs	1,197	26,624	4%
Number used as logic	1,036
Number used as a route-thru	42
Number used for Dual Port RAMs	16
Number used for 32x1 RAMs	52
Number used as Shift registers	51
Number of bonded IOBs	315	333	94%
IOB Flip Flops	54
Number of Block RAMs	9	32	28%
Number of MULT18X18s	1	32	3%
Number of GCLKs	3	8	37%
Number of DCMs	2	4	50%
Total equivalent gate count for design	630,981
Additional JTAG gate count for IOBs	15,120

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met